1. Field of Invention
The present invention relates to a method of fabricating a metal oxide semiconductor (MOS) transistor. More particularly, the present invention relates to a method for fabricating a self-aligned contact (SAC).
2. Description of Related Art
In a conventional method of fabricating a self-aligned contact (SAC), an insulating layer is formed on the sidewalls and top of a polysilicon gate on a substrate in order to serve as spacers. The spacers can protect the gate from being damaged during a step of forming a contact hole formed subsequently. Moreover, the spacers can provide a self-aligning function for the contact hole formed subsequently. An inter-layer dielectric (ILD) layer is formed over the substrate to cover the polysilicon gate. The ILD layer is defined to form a self-aligned contact hole. The self-aligned contact hole is filled with a polysilicon layer or a tungsten layer. A self-aligned contact is completely formed.
According to a design rule, before defining the ILD layer to form the contact hole, the conventional method is to reserve more space around the contact hole in order to avoid misalignment, leading to a decrease of contact area between the contact and the source/drain region. In order to increase the integration of devices, a borderless contact is normally used to efficiently reduce the size of device.
While forming a self-aligned borderless contact hole, if misalignment occurs, contact area between the contact and the source/drain region is reduced, that leads to increasing contact resistance between the contact and the source/drain region.
FIGS. 1A through 1E are schematic, cross-sectional views showing a conventional method of fabricating a self-aligned contact.
Referring to FIG. 1A, a P-type semiconductor substrate 100 is provided. A gate 102 is formed on the substrate 100. The steps of forming the gate 102 includes forming a gate oxide layer 104 on the substrate 100, forming a stacked conductive layer 106 on the gate oxide layer 104 and forming a cap layer 108 on the stacked conductive layer 106. The steps of forming the stacked conductive layer 106 includes forming a doped polysilicon layer (not shown) on the gate oxide layer 104 and forming a silicide layer (not shown) on the doped polysilicon layer. A lightly doped source/drain region 110 is formed by implanting N-type arsenic ions or phosphorus ions into the substrate 100, using the gate 102 as a mask.
Referring to FIG. 1B, a conformal insulating layer 114 is formed over the substrate 100 by chemical vapor deposition (CVD).
Referring to FIG. 1C, the insulating layer 114 is defined by photolithography and etching. A part of the insulating layer 114 on the substrate 100 is removed by an anisotropic etching method while the remaining part of the insulating layer 114 covers the surface of the gate 102. As shown in FIG. 1C, the remaining part of the insulating layer 114 is on the sidewalls and the top of the gate 102 to serve as spacers 114a. Due to the formation of the spacers 114a, a contact hole 115 having a self-aligning function is formed above the lightly doped source/drain region 110. The spacers 114a not only serve as protection for the gate 102, but also serve as a mask in the formation of heavily doped source/drain regions. Then, an ion implantation with heavily doped ions is performed to form a heavily doped source/drain region onto the substrate 100. A source/drain region 116 having a lightly doped drain (LDD) structure is thus formed.
Referring to FIG. 1D, a dielectric layer 120 is formed over the substrate 100 to cover the gate 102 by CVD.
The dielectric layer 120 is defined to form a contact hole 122 in the dielectric layer 122 by photolithography and etching. The source/drain region 116, which is normally below the expected contact hole 115, is exposed. However, the contact hole 122 is easily misaligned during the step of defining the dielectric layer 120. If misalignment occurs, the contact hole 122 is not completely aligned to the source/drain region 116. Only a portion of the spacers 114a and a portion of the source/drain region 116 are exposed by the misaligned contact hole 122. Thus, contact resistance between the source/drain region 116 and a plug formed subsequently is increased. If the misalignment occurs more seriously, an open condition caused by no contact between the contact and the source/drain region 116 occurs.
Referring to FIG. 1E, a plug 124 is formed in the contact hole 122 in the dielectric layer 120. The step of forming the plug 124 includes forming a glue/barrier layer (not shown) along the contact hole 122, in order to increase adhesion between a conductive layer formed subsequently and other material on the substrate 100. The glue/barrier layer includes titanium/titanium nitride (Ti/TiN) or tantalum/tantalum nitride (Ta/TaN). A conductive layer, such as a tungsten layer, is formed over the substrate 100 to fill the contact hole 122. The part of the conductive layer on the dielectric layer 120 is removed until the dielectric layer 120 is exposed by chemical mechanical polishing (CMP). Thus, the plug 124 is formed in the contact hole 122 and the plug 124 is electrically coupled to the source/drain region 116.
In the conventional method of forming the contact hole 122, misalignment easily occurs while forming the contact hole 122. The misalignment causes only a portion of the source/drain region 116 to be exposed by the contact hole 122. Therefore, contact resistance between the source/drain region 116 and the plug 124 formed is increased. If the misalignment is more serious, even an open condition caused by no contact between the contact and the source/drain region 116 occurs.